The present invention relates to a Test Adapter for actively testing an integrated circuit chip package in combination with a printed circuit board and a method for actively testing an integrated circuit chip package.
Integrated circuit (IC) chips are packaged in an insulating housing. The IC chip, the housing and a signal interface for coupling the IC chip to external components together comprise an IC chip package. The signal interface is critical to the operation of the IC chip package in that it allows the IC chip to interact with external circuit components so that the IC chip can perform meaningful functions. The signal interface must be capable of accommodating all of the electrical signals necessary to operate and communicate with the IC chip. With the continued miniaturization of IC chips, more and more circuit functions can be incorporated into a single chip. Correspondingly, with more and more circuit functions being performed, more and more I/O signals are necessary to operate the IC chips. Not only must larger numbers of signals be connected to the IC chip, but more and more signals must be connected in a smaller and smaller area. In general, IC chip packages are mounted on printed circuit boards which are crowded with other circuit elements, including other chip packages. In most cases, space on the printed circuit boards is limited, and it is beneficial that the signal interface take up as little space as possible. A ball grid array is such an interface.
Ball Grid Array (BGA) chip packages are surface mount devices which connect directly to the surface of a printed circuit board. A grid-like array of hemispherical solder balls is formed on the bottom of the chip package, and internal contact leads connect each solder ball to a different input or output point on the IC chip. On the surface of a printed circuit board, an array of conductive solder pads is formed corresponding to the array of solder balls formed on the chip package. The BGA chip package is placed on the printed circuit board over the solder pads, and placed in a re-flow oven where the solder balls are melted, bonding the BGA chip package to the printed circuit board. Conductive traces connected to the solder pads on the printed circuit board convey electronic signals to and from external circuit components mounted elsewhere on the printed circuit board.
An advantage of BGA chip packages is that the I/O interface is located directly below the chip package so that the interface does not occupy any additional space on the printed circuit board beyond the perimeter of the BGA chip package itself. This contrasts with other IC chip packages where the I/O signals exit through the edges of the chip package, or through pins protruding from the chip package. In these alternate IC chip packages, the interface is external to the outer periphery of the IC package, requiring additional space on the printed circuit board.
One disadvantage of BGA chip packages, however, is that they are difficult to test once they are bonded to the printed circuit board. Because the I/O interface is located directly beneath the chip package, it is not possible to connect test probes to the various signals leads once the chip package is bonded to the printed circuit board. Thus, it is difficult to actively test BGA chip packages in combination with the printed circuit boards they are designed to work with. This drawback is especially significant in the early design/testing stages of developing new products. In these early stages, flaws in the IC chip or the printed circuit board design can cause unexpected product malfunctions, and without the ability to access I/O signals for the purpose of attaching test probes, it is difficult to determine the cause of such malfunctions.
In many applications, active testing of printed circuit boards and IC chip packages is accomplished by applying various combinations of input signals to the printed circuit board and measuring the corresponding output signals to see if they behave as expected. Often, the only way to monitor such signals is to connect test probes at points on the printed circuit board where the signals are accessible. With most integrated circuit chip packages, the point where the I/O signals are most accessible is at the interface between the IC package and the printed circuit board. However, with BGA chip packages, because this interface is located directly beneath the BGA chip package, these points are not accessible for the purpose of landing test probes thereon. Thus, it is not possible to use traditional methods to actively test the operation of BGA chip packages in combination with the printed circuit boards to which they are mounted. One solution to this problem is to design test points into the printed circuit board. Using this method, conductive test points such as pins, or conductive pads are formed on the printed circuit board in locations where they are easily accessible, and conductive traces are formed on the printed circuit board connecting the test points to the various I/O signals, thereby providing a means to monitor the operation of the chip package and the printed circuit board. A major drawback of this method, however, is that it tends to defeat the purpose for using a BGA chip package in the first place, namely, saving space on the printed circuit board. Adding the test points and connections from the test points to the I/O signals can easily consume more board space than one of the alternate methods of mounting an IC package.
From the foregoing discussion, it is clear that a need exists for providing a mechanism for actively testing BGA chip packages in combination with the printed circuit board on which it is to be mounted. Such a mechanism must necessarily provide for the complete interconnection of the BGA chip package to the printed circuit board so that the combination operates the same as under normal conditions. The test mechanism must also provide accessible test points for at least a limited number of I/O signals from the BGA chip package so that the BGA chip package and printed circuit board can be monitored by measuring the active I/O signals. It is desirable that such a test mechanism would have test points in the form of contact pins to which probes are easily attached. It is also desirable to have test pins arranged into groups, or headers for easy connection to external test equipment. Such groupings could include ribbon cable headers, or pin grids, which are well known in the art and can be readily connected to other devices using existing connector hardware. Finally, it would be advantageous to provide a test mechanism where the test points are programmable such that any given test point can be programmed to connect to any given I/O point on the BGA chip package. This type of programmability would make such a test mechanism more versatile in that it could be used over and over with different BGA chip packages, and different printed circuit boards which require different I/O points to be monitored.